1. Field of the Invention:
This invention relates to a GaAs field effect transistor (hereinafter, referred to an FET for a field effect transistor) having a WSi schottky gate electrode, and more particularly to an improvement of the WSi (tangsten silicide) schottky gate electrode for a high-speed operation.
2. Description of the Related Art:
WSi has been conventionally used for a gate electrode of a junction gate FET having a high transfer-conductance, because WSi has a relatively small resistivity and is not damaged in a high-temperature process of 800.degree. C. or above. Especially, due to such property of WSi, the GaAs FET can be formed by a self-alignment process in which the gate WSi is used for a mask for forming source and drain regions by impurity ion-implantation. The use of the self-alignment process realizes a very small GaAs FET. Thus, a highly-integrated, high-speed logic IC can be obtained by using the WSi Schottky gate GaAs FET's.
However, WSi has a low resistivity, compared to polycrystalline Si, but it has a high resistivity, compared to Al. For example, WSi has a resistivity of 3.6 K.OMEGA./mm with a thickness of 0.5 .mu.m and a width of 1 .mu.m. This resistivity increases a paracitic gate resistance to decrease a switching speed of the FET or to deform the waveform of output pulse.
Especially, in order to produce a sufficient output voltage with a high-speed operation, it is required to use FET's having a wide gate electrode for a large current operation. If an output of 1 volt is required with a 50 ohms-load, the gate width of several hundreds .mu.m is necessary. For example, in a case where the FET has a WSi gate electrode having a thickness of 0.5 .mu.m, a gate length of 1.0 .mu.m and a gate width of 500 .mu.m, the parasitic gate resistance becomes an order of 2 K.OMEGA.. Such large gate resistance considerably affects the switching speed and the output waveform.
These degradations of switching speed and the output waveform are also affected from capacitances such as the capacitance accompanying with output wirings and the coupling capacitance existing between the FET itself and adjacent wirings. Particularly, in GaAs IC, the effect of the coupling capacitance is not ignorable, because the electric field from the FET widely extends through the semi-insulating substrate in which FET's are formed.
Under these circumstances, it is easily understood that, if the gate width is decreased, the FET can be made small to decrease the parasitic gate resistance and the coupling capacitance. This measure is accompanied by a decrease in operating current and does not give a complete solution for the degradations. The coupling capacitance depends on circuit design, wiring pattern, manufacturing condition and so on and is difficult to be controlled. Therefore, the relationship between the operational speed and the gate width has never been examined.